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Course Title:

Microelectronics - Design with VHDL - Laboratories

ClassWeb Code:

ΣΗΤ110

Code set by the department:

M414

Prerequisites:

-

Weak prerequisites

-

Kind:

Core

Category:

A

Hours:

6

Coordinator:

Papadopoulos Ioannis

ECTS:

9

(if registered since ac. year 2022-23)

9

(if registered from ac. year 2019-20 up to 2021-22)

9

(if registered from ac. year 2010-11 up to 2018-19)

Description:

• Introduction to CMOS circuits (VLSI, MOS, CMOS, BiCMOS). CMOS logic (inverter, NOR, NAND, Compound gates), multiplexers, memory, registers. Circuit representations. • MOS transistor theory, MOS device equations, CMOS inverter, SPICE simulation. • Silicon Semiconductor processing technology, basic CMOS technology, interconnect, circuit elements (capacitors, resistors), layout design rules, Latchup. • Circuit characterization and performance estimation, resistance-capacitance- inductance estimation • Switching characteristics, delay models, transistor sizing • Power dissipation, sizing routing conductors, charge sharing, design margining, process variations and yield • CMOS circuit physical and logic design (inerter, NOR, NAND, NOR, XOR, complex logic gates layout) • Transmission gate layout, Dynamic logic, clocking systems, input-output structures, overall organization of the physical design-Low power design. • Laboratories: Design-simulation software, CMOS custom design examples (inverter, NAND, NOR, XOR, complex logic gates, dynamic logic and memories) • VHDL design techniques for PLDs, simulation and implementation. In particular: ◦ Technologies of PLDs ◦ circuit design ◦ Synthesis, design levels of abstraction, simulation. ◦ XILINX ISE Design Suite. ◦ An Introduction to VHDL: -- entities, architecture, operators, simulation examples of logic gates and Boole functions -- concurrent VHDL: signals, delays, objects, classes, data types, concurrent statements, operators -- sequential VHDL: signals and variables, processes, components, statements -- Libraries, subprograms, functions, procedures, packages, attributes -- Structural VHDL: component, port map, generic map, configuration, Examples.

Remarks:

none

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